MR. KIRK GRAY

Kirk Gray has over thirty two years of experience in the electronics manufacturing industry. Mr. Gray began his career in electronics at the semiconductor level and followed the manufacturing process as a Manager in Engineering Test.  As a field engineer for Accelerators Inc. and Veeco Instruments from 1977 to 1982, he installed and serviced, helium mass spectrometers (leak detection), Ion Implantation Systems, and many other thin-film, high vacuum systems used in semiconductor fabrication. As a Sales Engineer for Veeco Instruments and CVC from 1982 through 1986, he worked with semiconductor process engineers to solve thin-film application and etching process issues and equipment applications. 

As the Environmental Stress Screening (ESS) Process Engineering Manager in manufacturing test at Storage Technology from 1989 to 1992, he worked with Dr. Gregg K. Hobbs, the inventor of the terms and techniques of Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS).  Mr. Gray's ESS process engineering team applied the HALT and HASS process and procedures into existing manufacturing production of data storage systems. He recognized, documented and promoted the tremendous benefits of HALT and HASS in the design and production of electronics and electro-mechanical systems. In the spring of 1992 in Vancouver, Washington, Mr. Gray was an invited speaker to the first Institute of Environmental (IES) Workshop on Environmental Stress Screening of Electronic Hardware. He presented a seminar and paper on "Stress Screen Design" at StorageTek using HALT and HASS.

In 1994 John formed AcceleRel Engineering, Inc. a consulting company. He led a wide variety of electronic companies including the bio-medical, telecommunications, power supply, and other electronic systems producers, to methods of HALT and HASS and rapidly improving reliability of electronic and electro-mechanical hardware. He has been invited worldwide to teach and consult HALT and HASS and the Physics-of-Failure (PoF) approach to reliability. Mr. Gray has help plan and has helped direct testing, developed test fixtures, optimized accelerated stress screen thermal cycling, analyzed test data, created written test reports advised design teams on component layout for robust assemblies. He also conducted failure analysis of assemblies and components to root-cause. Mr. Gray has documented results of reduced warranty return rates from 5% to 0.5% after new test processes were applied. With this 90% reduction in warranty returns, reliability testing was reduced from 72 hours to one (1) hour. He developed recommendations for maintenance and improvement of accelerated reliability screening methods for continued production test efficiency.

From 2003 until 2010 Kirk was a Sr. Reliability Validation Engineer at Dell, Inc. where he created new HALT based test processes for desktop and portable computers. He created, wrote and implemented the HALT to HASA process on power supply systems. The HASA process was recognized for being the highest ROI (Return on Investment) of all the many ongoing reliability processes for its ability to rapidly detect process excursions. He developed new thermal cycling tests that quickly reproduced the intermittent operational failure mode that was the cause of a field return, after 5 days of traditional Failure Analysis had resulted in a CND (Cannot Duplicate) status. Mr. Gray’s test exposed the defect and underlying cause as he reproduced the customer complaint three times in 23 hours.

Mr. Gray has co-authored the article in the September 2000 issue of Evaluation Engineering Magazine  "Don't Let the Cost of HALT Stop You" with Mr. Wayne Tustin.

He presented the Professional Education Seminar "HALT and HASS: Methods That Work" at the 2002 Applied Power Electronics Conference  held in Dallas, Texas, March 10-14, 2002.

Mr. Gray is the Past Chairman of the Denver Chapter of the IEEE Reliability Society. He is a charter member and past Chairman of the IEEE/CPMT Technical Committee on Accelerated Stress Testing and Reliability . He is a Charter Member and the AST Workshop Webmaster of the  IEEE/CPMT Accelerated Stress Testing (TC-7) Steering Committee. 

He earned a Bachelor of Science degree in Electrical Engineering from the University of Texas at Austin in1982.